Siemens Medical Systems UltraSound Group Service Software


// begin playback from c:\zdt\serviceScripts\sam2zdtTestScript634d127_0_0_13.dui
Start Time : Mon Mar 26 11:53:57 2012

Orchid Common  Events Stop Monitors Event
Set Common  Events value to 1
EXECUTED
 
Orchid Common  Events Stop Monitors Event
EXECUTED
 
Orchid Receive Control Rc Memory test
PASS
 
Orchid Receive Control Rc Memory test
EXECUTED
 
Orchid Receive Control Rc Memory test
PASS
 
Orchid Receive Control Rc Memory test
EXECUTED
 
Orchid Front End BIT Sequence Test
PASS
 
Orchid Receive Control Register Access
Writing 0x1 to Receive Control Sequence Stop
EXECUTED
 
Orchid Receive Beamformer ASIC 0 ZbRxbf Memory test
PASS
 
Orchid Receive Beamformer ASIC 1 ZbRxbf Memory test
PASS
 
Orchid Receive Beamformer ASIC 2 ZbRxbf Memory test
PASS
 
Orchid Receive Beamformer ASIC 3 ZbRxbf Memory test
PASS
 
Orchid Receive Control Register Access
Writing 0x1 to Receive Control Sequence Stop
EXECUTED
 
Orchid Receive Beamformer ASIC 0 ZbRxbf BIST Test
Opening file "C:\Zdt\zbrxbf_bist.txt"
PASS
 
Orchid Receive Beamformer ASIC 1 ZbRxbf BIST Test
Opening file "C:\Zdt\zbrxbf_bist.txt"
PASS
 
Orchid Receive Beamformer ASIC 2 ZbRxbf BIST Test
Opening file "C:\Zdt\zbrxbf_bist.txt"
PASS
 
Orchid Receive Beamformer ASIC 3 ZbRxbf BIST Test
Opening file "C:\Zdt\zbrxbf_bist.txt"
PASS
 
Orchid Receive Control Register Access
Writing 0x1 to Receive Control Sequence Stop
EXECUTED
 
Orchid Digital Receiver ASIC 0 Dr Bist test
PASS
 
Orchid Digital Receiver ASIC 1 Dr Bist test
PASS
 
Orchid Receive Control Register Access
Writing 0x1 to Receive Control Sequence Stop
EXECUTED
 
Orchid Digital Receiver ASIC 0 Dr Memory test
PASS
 
Orchid Digital Receiver ASIC 1 Dr Memory test
PASS
 
Orchid Receive Control Register Access
Writing 0x1 to Receive Control Sequence Stop
EXECUTED
 
Orchid Txpg ASIC 0 Memory Test
BE Bar 0 0x8478840 Register Address Error in Txpg ASIC 0 Synchronous Command Word Register expected 0x0 actual 0x4
FAIL
 
Orchid Txpg ASIC 0 txpg RAM test
BE Bar 0 0x8478000 Table Data Error in Txpg ASIC 0 Static RAM [0]  expected 0xaaaa actual 0x4
FAIL
 
Orchid Txpg ASIC 1 Memory Test
BE Bar 0 0x8479840 Register Data Error in Txpg ASIC 1 Synchronous Command Word Register  expected 0x1 actual 0x0
FAIL
 
Orchid Txpg ASIC 1 txpg RAM test
BE Bar 0 0x8479000 Table Data Error in Txpg ASIC 1 Static RAM [0]  expected 0xaaaa actual 0x0
FAIL
 
Orchid Txpg ASIC 2 Memory Test
BE Bar 0 0x847a840 Register Address Error in Txpg ASIC 2 Synchronous Command Word Register expected 0x0 actual 0x4
FAIL
 
Orchid Txpg ASIC 2 txpg RAM test
BE Bar 0 0x847a000 Table Data Error in Txpg ASIC 2 Static RAM [0]  expected 0xaaaa actual 0x4
FAIL
 
Orchid Txpg ASIC 3 Memory Test
BE Bar 0 0x847b840 Register Data Error in Txpg ASIC 3 Synchronous Command Word Register  expected 0x1 actual 0x0
FAIL
 
Orchid Txpg ASIC 3 txpg RAM test
BE Bar 0 0x847b000 Table Data Error in Txpg ASIC 3 Static RAM [0]  expected 0xaaaa actual 0x0
FAIL
 
Orchid Receive Control Register Access
Writing 0x1 to Receive Control Sequence Stop
EXECUTED
 
Orchid Txpg ASIC 0 txpg Self-test
BIST timeout  
FAIL
 
Orchid Txpg ASIC 1 txpg Self-test
BIST timeout  
FAIL
 
Orchid Txpg ASIC 2 txpg Self-test
BIST timeout  
FAIL
 
Orchid Txpg ASIC 3 txpg Self-test
BIST timeout  
FAIL
 
Orchid Receive Control Register Access
Writing 0x1 to Receive Control Sequence Stop
EXECUTED
 
Orchid Transmit Receiver Tr Memory test
BE Bar 0 0x8468018 Register Address Error in Transmit Receiver Diagnostic Control Register expected 0x0 actual 0x4
BE Bar 0 0x8468020 Register Address Error in Transmit Receiver I2C Control Register expected 0x0 actual 0x4
BE Bar 0 0x8468024 Register Data Error in Transmit Receiver ID Prom Rd Address Register  expected 0xff00 actual 0x0
BE Bar 0 0x846802c Register Address Error in Transmit Receiver ID Prom Write Register expected 0x0 actual 0x4
FAIL
 
Orchid Transducer Interface Ti Memory test
PASS
 
Orchid Front End BIT Receive Test
PASS
 
Orchid Front End BIT Transmit Test
FAIL
 
Orchid Transducer Interface Register Access
Writing 0x1 to Transducer Interface Global Control
EXECUTED
 
Orchid Transmit Receiver Register Access
Writing 0x1 to Transmit Receiver Global Control
EXECUTED
 
Orchid Front End BIT Diag A2D Test
EXECUTED
 
Orchid Front End BIT Diag A2D Test
EXECUTED
 
Orchid Front End BIT Diag A2D Test
EXECUTED
 
Orchid Front End BIT Diag A2D Test
EXECUTED
 
Orchid Front End BIT Diag A2D Test
EXECUTED
 
Orchid Front End BIT Diag A2D Test
EXECUTED
 
Orchid Front End BIT Diag A2D Test
EXECUTED
 
Orchid Front End BIT Diag A2D Test
EXECUTED
 
Orchid Front End BIT Diag A2D Test
EXECUTED
 
Orchid Front End BIT Diag A2D Test
EXECUTED
 
Orchid Front End BIT Diag A2D Test
EXECUTED
 
Orchid Front End BIT Diag A2D Test
EXECUTED
 
Orchid Front End BIT Diag A2D Test
EXECUTED
 
Orchid Front End BIT Diag A2D Test
EXECUTED
 
Orchid Front End BIT Diag A2D Test
EXECUTED
 
Orchid Front End BIT Diag A2D Test
EXECUTED
 
Orchid Front End BIT Diag A2D Test
EXECUTED
 
Orchid Front End BIT Diag A2D Test
EXECUTED
 
Orchid Front End BIT Diag A2D Test
EXECUTED
 
Orchid Front End BIT Diag A2D Test
EXECUTED
 
Orchid Front End BIT Diag A2D Test
EXECUTED
 
Orchid Front End BIT Diag A2D Test
EXECUTED
 
Orchid Front End BIT Diag A2D Test
Ch  2 Brd 0 VMID  - A2D Mid range voltage         =    0.00 (   0.90 to    1.10) fail  
Ch  1 Brd 0 VFC1                                  =    0.00 (   0.72 to    0.88) fail  
Ch  3 Brd 0 VCM     - RCFEREF TR buffered ver.    =    0.00 (   0.90 to    1.10) fail  
Ch  4 Brd 0 P3.3_D  - 3.3 Volt Digital            =    0.00 (   3.06 to    3.40) fail  
Ch 14 Brd 0 P5_AC   - P5 Analog                   =    0.00 (   4.59 to    5.41) fail  
Ch 13 Brd 0 M2_AR1  - Negative 2 Volt Pwr         =    0.00 (  -2.20 to   -1.80) fail  
FAIL
 
Orchid VpDm Dopper Audio Test
EXECUTED
 
Orchid VpDm Dopper Audio Test
PASS
 
Orchid SIP in Df FPGA DSP Ipc test
PASS
 
Orchid Receive Control Register Access
Writing 0x1 to Receive Control Sequence Stop
EXECUTED
 
Orchid Rmp FPGA Rmp FPGA Memory test
PASS
 
Orchid Receive Control Register Access
Writing 0x1 to Receive Control Sequence Stop
EXECUTED
 
Orchid Echo Processor ASIC Mp Ep Memory test
PASS
 
Orchid Receive Control Register Access
Writing 0x1 to Receive Control Sequence Stop
EXECUTED
 
Orchid Echo Processor ASIC Mp Ep Bist test
Opening file "C:\Zdt\zbmpep_bist.txt"
PASS
 
Orchid Receive Control Register Access
Writing 0x1 to Receive Control Sequence Stop
EXECUTED
 
Orchid Flow Processor ASIC Fp Memory test
PASS
 
Orchid Receive Control Register Access
Writing 0x1 to Receive Control Sequence Stop
EXECUTED
 
Orchid Flow Processor ASIC Fp CtbMemory test
PASS
 
Orchid Receive Control Register Access
Writing 0x1 to Receive Control Sequence Stop
EXECUTED
 
Orchid Fp in Df FPGA Fp FPGA Memory test
PASS
 
Orchid Receive Control Register Access
Writing 0x1 to Receive Control Sequence Stop
EXECUTED
 
Orchid Fp in Df FPGA Fp FPGA Memory test
PASS
 
Orchid Receive Control Register Access
Writing 0x1 to Receive Control Sequence Stop
EXECUTED
 
Orchid Scan Converter ASIC Sc Memory test
PASS
 
Orchid Receive Control Register Access
Writing 0x1 to Receive Control Sequence Stop
EXECUTED
 
Orchid Scan Converter ASIC Sc External SDRAM Test
PASS
 
Orchid Receive Control Register Access
Writing 0x1 to Receive Control Sequence Stop
EXECUTED
 
Orchid SIP in Df FPGA SIP Memory test
PASS
 
Orchid Receive Control Register Access
Writing 0x1 to Receive Control Sequence Stop
EXECUTED
 
Orchid SIP DSP DSP Memory test
PASS
 
Orchid Receive Control Register Access
Writing 0x1 to Receive Control Sequence Stop
EXECUTED
 
Orchid VI Decoder Vi Decoder FPGA Memory Test
PASS
 
Orchid VI Encoder Vi Encoder FPGA Memory Test
PASS
 
Orchid VpDm VpDm Memory Test
PASS
 
Orchid Orchid System B Mode System Test
Scaling data...
FAIL Orchid Orchid System BC Mode System Test Scaling data... FAIL Orchid Control Panel Status test CP test OK. PASS Test Summary : FAIL Mon Mar 26 11:58:34 2012 // end playback from c:\zdt\serviceScripts\sam2zdtTestScript634d127_0_0_13.dui